1. Field of the Invention
The embodiments of the invention generally relate to dual work-function gate electrodes and, more particularly, to dual work-function gate electrodes on dual-plane high-mobility complementary metal oxide semiconductor devices.
2. Description of the Related Art
Recently, to enhance carrier mobility and, thus, performance of complementary metal oxide semiconductor (CMOS) devices, p-type field effect transistors (p-FETs) and n-type field effect transistors (n-FETs) have been formed on different planes within the same semiconductor layer. That is, to enhance performance CMOS devices have been formed that comprise different type devices: one with sidewall channels and one with a planar channel. Specifically, such a CMOS device can comprise a non-planar first type transistor (e.g., a p-FET) with a channel region that is perpendicular relative to the substrate (i.e., sidewall channels) so that it has a first orientation (e.g., a 110 orientation that is optimal for mobility of first type carriers (e.g., holes)). Gates are formed on the opposing sidewalls and, optionally, on the top and bottom surfaces of the channel region. Additionally, the CMOS device can comprise a planar second type transistor (e.g., an n-FET) with a channel region that is parallel relative to the substrate so that it has a second orientation (e.g., 100 orientation that is optimal for mobility of second type carriers (e.g., electrons)) and a single gate above the channel region and, optionally, a back gate below the channel region.
Performance of CMOS devices has also been enhanced by incorporating dual work-function gate electrodes into the CMOS device structure. That is, CMOS devices have been formed that comprise gate electrodes that have different materials selected to optimize p-FET performance and n-FET performance, respectively. Specifically, gate electrodes can be formed from polysilicon and doped with different type dopants (e.g., n-type or p-type dopants) to different degrees, depending upon the type of field effect transistor being formed. Alternatively, gate electrodes can be formed from different metal materials, depending upon the type of field effect transistor being formed. For example, it is desirable for the work function of gate electrodes on n-FETs to be close to the conduction band in order to reduce the threshold voltage of such transistors and, thereby, optimize n-FET drive current. This can be accomplished by doping a polysilicon gate electrode of an n-FET with a high concentration of an n-type dopant (e.g., phosphorous (P), arsenic (As) or antimony (Sb)). This can also be accomplished by forming the gate electrode with a conduction band metal (e.g., aluminum (Al)). Contrarily, it is desirable for the work function of gate electrodes on p-FETs to be close to the valence band in order to reduce the threshold voltage of such transistors and, thereby, optimize p-FET drive current. This can be accomplished by doping a polysilicon gate electrode of a p-FET with a high concentration of a p-type dopant (e.g., boron (B)). This can also be accomplished by forming the gate electrode with a valence band metal (e.g., magnesium (Mg)).
While prior art CMOS devices have incorporated dual work-function gate electrodes as well as planar and non-planar FETs, the methods used to form such devices are costly, requiring a number of additional processing steps, including multiple gate masks. Therefore, there is a need in the art for an improved simple dual-plane high-mobility CMOS device structure and method of forming the structure that requires only a single gate mask.